Espressif Systems /ESP32 /SPI0 /SLAVE

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Interpret as SLAVE

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SLV_RD_BUF_DONE)SLV_RD_BUF_DONE 0 (SLV_WR_BUF_DONE)SLV_WR_BUF_DONE 0 (SLV_RD_STA_DONE)SLV_RD_STA_DONE 0 (SLV_WR_STA_DONE)SLV_WR_STA_DONE 0 (TRANS_DONE)TRANS_DONE 0INT_EN0CS_I_MODE 0SLV_LAST_COMMAND 0SLV_LAST_STATE 0TRANS_CNT 0 (SLV_CMD_DEFINE)SLV_CMD_DEFINE 0 (SLV_WR_RD_STA_EN)SLV_WR_RD_STA_EN 0 (SLV_WR_RD_BUF_EN)SLV_WR_RD_BUF_EN 0 (MODE)MODE 0 (SYNC_RESET)SYNC_RESET

Fields

SLV_RD_BUF_DONE

The interrupt raw bit for the completion of read-buffer operation in the slave mode.

SLV_WR_BUF_DONE

The interrupt raw bit for the completion of write-buffer operation in the slave mode.

SLV_RD_STA_DONE

The interrupt raw bit for the completion of read-status operation in the slave mode.

SLV_WR_STA_DONE

The interrupt raw bit for the completion of write-status operation in the slave mode.

TRANS_DONE

The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.

INT_EN

Interrupt enable bits for the below 5 sources

CS_I_MODE

In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter.

SLV_LAST_COMMAND

In the slave mode it is the value of command.

SLV_LAST_STATE

In the slave mode it is the state of spi state machine.

TRANS_CNT

The operations counter in both the master mode and the slave mode. 4: read-status

SLV_CMD_DEFINE

1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer.

SLV_WR_RD_STA_EN

write and read status enable in the slave mode

SLV_WR_RD_BUF_EN

write and read buffer enable in the slave mode

MODE

1: slave mode 0: master mode.

SYNC_RESET

Software reset enable, reset the spi clock line cs line and data lines.

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